1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a capacitor formed in a multilayer wiring structure.
2. Description of the Related Art
Various semiconductor devices having a multilayer wiring structure are used. It is known that recent interconnection wiring used in the multilayer wiring structure of such a semiconductor device are composed of materials such as aluminum (Al) and copper (Cu). Different methods are used to form the interconnection wiring depending on whether or not these materials can be easily subjected to exposure, etching, or the like. In particular, if copper is used for the interconnection wiring, it has the advantages of offering smaller resistance than aluminum, hindering electromigration more excellently than aluminum, and the like. While, if copper is used for the interconnection wiring, it is known to be disadvantages in that it is diffused in silicon (Si) and silicon oxide (SiO2) at a very high rate, in that it cannot be formed into a film properly using a CVD process, and in that it cannot be dry-etched.
Thus, a single damascene process or a dual damascene process is used to form the copper interconnection wiring, in order to be realized the advantages of the copper as used in the interconnection wiring, while effectively eliminating the disadvantages of copper as formed in the silicon (Si) and silicon oxide (SiO2). In particular, using the dual damascene process, a via hole and a wiring groove portion connected to the via hole can be sequentially etched in an insulating film in a multilayer wiring layer. Subsequently, copper can be buried in the via hole and the wiring groove portion at the same time. The dual damascene process reduces the number of processes executed, thus enabling manufacturing costs to be reduced.
On the other hand, for capacitors used in analog circuits or the like, what is called a “MIM capacitor”, composed of a metal film, a dielectric film, and a metal film, has been used in place of a polysilicon capacitor in order to improve capacitive accuracy. Description will be given below of an example of a conventional process of forming such a semiconductor device.
Such a semiconductor device has a multilayer wiring structure including, for example, a MOS transistor formed on a semiconductor substrate. The semiconductor device has a MIM capacitor formed in a predetermined wiring later in this multilayer wiring structure.
When a semiconductor device having such a structure is manufactured, first, a gate insulating film and a gate electrode of a MOS transistor are sequentially formed, by exposure and etching, on a semiconductor substrate between element isolation insulating films formed in the substrate. Then, an impurity ion injecting process is executed to form source/drain areas in the semiconductor substrate on the both sides of the gate insulating film and the gate electrode. Subsequently, a CVD process is used to form a first interlayer insulating film of SiO2 covering the whole semiconductor substrate including the gate insulating film and the gate electrode. Then, the surface of the first interlayer insulating film is flattened using a CMP process.
Subsequently, the first interlayer insulating film located on one of the source/drain areas is etched so as to form a contact hole. Thus, a contact is formed which contacts with the top surface of the source/drain area. Furthermore, a second interlayer insulating film is deposited on the first interlayer insulating film. Then, a first wiring groove is etched in the second interlayer insulating film so as to connect to the contact. Copper is buried in the first wiring groove and then flattened using the CMP process, to form a first copper wiring. Then, a first copper diffusion stopper layer is deposited on the first copper wiring formed in the first interlayer insulating film.
Then, in an area of the semiconductor substrate different from that in which the MOS transistor has been formed, on the first copper diffusion stopper layer, a lower metal film (of a lower electrode), a dielectric film, an upper metal film (of an upper electrode), and a cap material film are sequentially deposited as a MIM capacitor.
Subsequently, the cap material film and the upper metal film are etched in order to form the upper electrode. Furthermore, the dielectric film and the lower metal film are etched in order to form the lower electrode. Then, a third interlayer insulating film is formed so as to cover all of the lower electrode, the dielectric film, the upper electrode, and the cap material film.
Subsequently, a wiring groove is formed in the third interlayer insulating film so as to connect to the upper electrode. Further, a via hole is formed in the third interlayer insulating film. The via hole leads to the lower electrode. A wiring groove is also formed which is connected to the via hole. In this case, a via hole and a wiring groove connected to the via hole may also be formed, as required, in the third interlayer insulating film formed on the area in which the MOS transistor is formed. Copper is deposited in these via holes and wiring grooves at the same time.
Subsequently, fourth and fifth wiring layers having similar configurations are formed on the third interlayer insulating film as required.
These steps complete a semiconductor device having a multilayer wiring structure in which a capacitor and copper wrings are formed in the wiring layers.
In the conventional manufacturing process for the conventional semiconductor device as described above, when a copper wiring is formed on the upper electrode of the MIM capacitor, the etching of the wiring groove may expose, undesirably, a part of the upper electrode or the etching may further proceed to expose even a part of the lower electrode. As a result, the copper wiring layer may undesirably be connected to the upper electrode or the lower electrode. Furthermore, even if the upper and lower electrodes are avoided to be exposed, if the wiring groove is etched down to the vicinity of either of these electrodes, then the copper wiring formed in this wiring groove may stress the electrodes, resulting in a crack thereof. As a result, the upper and lower electrodes may be short-circuited via the copper wiring to cause a leakage current. In other cases, a crack in the electrode may cause a defect in connections to degrade the functions of the MIM capacitor.